Lateral high-voltage devices with optimum variation lateral flux by using field plate

ABSTRACT

A semiconductor lateral voltage-sustaining region and devices based thereupon. The voltage-sustaining region is made by using the Metal-Insulator-Semiconductor capacitance formed by terrace field plate to emit or to absorb electric flux on the semiconductor surface, so that the effective electric flux density emitted from the semiconductor surface to the substrate approaches approximately the optimum distribution, and a highest breakdown voltage can be achieved within a smallest distance on the surface. The field plates can be either floating ones, or connected to floating field limiting rings. Coupling capacitance between different plates can also be used to change the flux distribution.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices. Morespecifically, the present invention relates to the surfacevoltage-sustaining region, i.e., the drift region of lateralhigh-voltage devices. The present invention also relates to edgetermination techniques of semiconductor high-voltage vertical devices.

BACKGROUND OF THE INVENTION

It has been pointed out in Ref. [1, 2], that one can use optimumvariation lateral doping, shortly as VLD, to achieve highest breakdownvoltage within a minimum distance on the surface. The breakdown voltagereached by using such method is close to the breakdown voltage of aone-sided abrupt parallel plane junction made by the same substrate.Furthermore, the methods of implementation of high-side devices as wellas low-side devices by using optimum VLD were proposed in references [4,5].

It has been proposed in Ref. [3] that the idea of optimum VLD, in itssubstantial physical mechanism, should be changed to optimum VLF, whereF stands for flux density. A method to realize an optimum VLF has alsobeen proposed in Ref. [3]. This method includes a film of highpermittivity material covering on the semiconductor surface.

However, most popular technologies of integrated circuits are CMOS andBiCMOS technologies, and in such technologies, few can provide thenecessary doses as well as depths of n-type and p-type impuritiesrequired according to Ref. [2] and [3]. Not to mention, almost notechnology in integrated circuits contain a process to fabricate amaterial of a permittivity much higher than that of the semiconductor asrequired in Ref. [3]. Therefore, it is interesting to find a method torealize optimum VLF in a lateral voltage-sustaining region byconventional CMOS/BiCMOS technologies so that the high-voltage or powerintegrated circuits can be made cost-effectively.

The present invention provides a method to realize optimum variationlateral flux density by using the multiple insulator layers and themultiple conductive layers inherently contained in the conventionalCMOS/BiCMOS technologies.

REFERENCES

-   [1] X. B. Chen, et al., “Lateral high-voltage devices using an    optimized variational lateral doping”, Int. J. Electronics, Vol. 80,    No. 3, pp. 449-459 (1996).-   [2] X. B. Chen, U.S. Pat. No. 5,726,469 or Chinese patent ZL    95108317.1.-   [3] X. B. Chen, U.S. Pat. No. 6,936,907 or Chinese patent ZL    02142183.8.-   [4] X. B. Chen, U.S. Pat. No. 6,310,365 B1.-   [5] X. B. Chen, U.S. Pat. No. 6,998,681 B2.

SUMMARY OF THE INVENTION

This invention is to take the advantages of the multiple insulatorlayers and the multiple conductive layers inherently contained in modernCMOS or BiCMOS technologies, to form a kind of terrace field plate.Since a specific capacitance between such field plates and thesemiconductor surface varies with distance, it can absorb differentelectric flux densities from different places of the semiconductorsurface, or emit different electric flux densities to different placesof the semiconductor surface. Here, the specific capacitance stands forthe capacitance in unit area. Based upon this principle, the electricflux density emitted from the surface voltage-sustaining region can beso modified that it approaches the ideal electric flux density describedin Ref. [3]. Thus, the surface voltage-sustaining region can yield abreakdown voltage close to that of the one-sided abrupt parallel-planejunction made by the same substrate.

The field plates can be floating, and then each of them has no electriccharge as a whole. The electric flux absorbed or emitted by each fieldplate can be in turn offset by charge or discharge of the couplingcondenser made by itself and the neighboring floating field plate. Themethods of establishing such coupling condenser are also presented inthis invention.

There are some possible reasons to make a floating field plate beingcharged. For instance, after the insulating layers have absorbedirradiation, or after some local areas have suffered to having highelectric field and being breakdown. In order to eliminate such charges,one method is to connect each floating field plate to a certain floatingfield limiting ring. Then, when the device is turned-on with the voltageacross the voltage-sustaning region being very low or when the devicehas not been applied any voltage, the potentials of all field plates areclose to the potential of the substrate and the charges on the fieldplates can be released.

With the surface voltage-sustaining region using floating field plates,not only low-side high voltage lateral devices can be made, but alsohigh-side high voltage lateral devices can be made.

This invention not only can be used to lateral devices, such as lateralMOSTs, diodes, etc., but also can be used as an edge terminationtechnique for vertical devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows schematically the structure, the flux density and thepotential distribution of the surface voltage-sustaining region of thelateral device.

FIG. 1( a) shows the structure of a lateral power device.

FIG. 1( b) shows the relationship between the electric flux density andthe distance to the location of the maximum potential.

solid line—the ideal flux density;

dash line—the flux density, qD₀, produced by the n-type region;

shaded area—the flux density need to be extracted from the surface (Thevoltage-sustaining region is divided to be four subregions, each has thesame width. The average flux densities need to be extracted arerepresented by ΔF₁, ΔF₂, ΔF₃ and ΔF₄, respectively);

FIG. 1( c) shows the potential distribution V(x) of the surfacevoltage-sustaining region in an ideal case, where the potential of theun-depleted neutral region of the p-type substrate is taken asreference.

FIG. 2 shows a lateral MOST where field plates are used to absorb theelectric flux from the semiconductor surface.

FIG. 2( a) shows the structure of the lateral MOST;

FIG. 2( b) shows the top view of the field plate, which has fourdifferent sections with different fill factor to produce four MIScapacitors with different average values;

FIG. 2( c) shows the equivalent circuit of the field plate having fourdifferent capacitances C₁, C₂, C₃ and C₄ connected to differentpotential V₁, V₂, V₃ and V₄, respectively.

FIG. 3 shows a structure of a lateral MOST with one terrace field platein its surface voltage-sustaining region. There are four layers withdifferent thickness of dielectric material to separate the semiconductorand the field plate.

FIG. 4 shows some examples of lateral MOST using different floatingfield plates.

FIG. 4( a) shows one grounded terrace field plate (104) and threesections of floating field plates (107, 108 and 109) under it.

FIG. 4( b) shows one grounded terrace field plate (104) and two sectionsof terrace floating field plates (110 and 111) as well as one section offloating field plate (107).

FIG. 5 shows some examples of lateral diode using multiple terracefloating field plates and one grounded field plate (Note that couplingcapacitances between plates exist because there are overlap regionsbetween plates):

FIG. 5( a) shows each terrace floating field plate are stepped up in thedirection towards to the anode terminal A;

FIG. 5( b) shows a method for increasing coupling capacitance betweenthe neighbouring floating field plates close to anode A and forincreasing coupling capacitance between a floating field plate and thesubstrate;

FIG. 5( c) shows each terrace floating field plate is stepped down inthe direction towards to the anode terminal A.

FIG. 6 shows an equivalent circuit for calculating the parameters offloating field plates shown in FIG. 5.

FIG. 7 shows a semiconductor lateral diode where terrace floating fieldplates are used to introduce electric flux to the semiconductor surface:

FIG. 7( a) shows each terrace floating field plate is stepped down inthe direction towards to the anode A;

FIG. 7( b) shows each terrace floating field plate is stepped up in thedirection towards to the anode A;

FIG. 7( c) shows an equivalent circuit for deriving the parameters ofthe floating field plates.

FIG. 8 shows a semiconductor lateral diode with interdigitated layoutwhere field plates are connected to the floating field limiting rings;

FIG. 8( a) shows the structure of semiconductor lateral diode, wherep⁺-type floating field limiting rings are set in the n-type region ofthe voltage-sustaining region;

FIG. 8( b) shows the cross-section view of the finger edge of theinterdigitated layout where no floating field limiting rings are set;

FIG. 8( c) shows the top view of the finger end of the interdigitatedlayout where floating field limiting rings are set.

FIG. 9 shows the cross-section view of a lateral MOST withinterdigitated layout having terrace field plates

FIG. 9( a) shows the structure at the finger edge of the interdigitatedlayout;

FIG. 9( b) shows the structure at the finger end of the interdigitatedlayout.

FIG. 10 shows the field plates of a device (202) having a large areaconnected to the field plates of a device (201) having a small area andthe latter are in turn connected to the floating field limiting rings ofthe device 201 itself;

FIG. 10( a) shows the structures of both devices, where 201 has a smallround layout and 202 has a large interdigitated layout.

FIG. 10( b) shows the top view of both devices.

FIG. 11 shows schematically the structures of a high-side MOST and alow-side MOST having a common n-type substrate and using terrace fieldplates and floating field limiting rings forming the surface voltagesustaining regions.

FIG. 12 shows schematically the structures of a high-side MOST and alow-side MOST different to FIG. 11 in that there is a thin insulatorlayer I between the substrate and the surface voltage-sustaining region.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1( a) shows schematically the structure of a lateral MOST, wherep⁻-region 001 is the substrate, n-region 011 is the surfacevoltage-sustaining region, also called drift region, D, S and G standfor drain, source and gate electrodes respectively. The shaded area 101is the gate oxide layer or the gate insulator layer. D is connected ton⁺-drain region 012, S is connected to n⁺-source region 013 which isconnected to p⁺-source contact region 014 and thus connected top⁻-substrate region 001. According to Ref. [1] and [2], in the idealcase, the electric flux density produced by the n-typevoltage-sustaining region is F(x) shown as solid line in FIG. 1( b),where the x-axis is shown in FIG. 1( a). F(x) has its maximum value,about 2ε_(s)V_(B)/W_(pp), at the place x=0, where ε_(s) is thepermittivity of the semiconductor, V_(B) is the breakdown voltage andW_(pp) is the thickness of the depletion layer of a one-sided abruptparallel-plane junction with the same substrate under the breakdownvoltage V_(B). Assuming the real technology can produce an average donordensity of n-region 011 being D₀, then the electric flux density is qD₀,which is shown as dash-line in FIG. 1( b). The dash-line has a verticaldistance to the solid-line, and the shaded area between these two linesin the figure illustrate the difference between the ordinates of bothlines. Assuming the voltage-sustaining n-region 011 is divided into fourequal distance sections and each has a width of d, then the averagedifference of the electric fluxes densities are ΔF₁, ΔF₂, ΔF₃ and ΔF₄,respectively. According to the purpose of this invention, the fluxcorresponding to ΔF₁, ΔF₂, ΔF₃ and ΔF₄ are excess ones and should beeliminated through the charging of the condenser on the surface of thesemiconductor. FIG. 1( c) shows potential distribution V(x) on the planeof y=0 in the ideal case, where the potential of the un-depleted neutralregion of the p⁻-substrate, 001, is taken as reference, i.e., V=0. Theordinate y has been shown in FIG. 1( a). V₁, V₂, V₃ and V₄ in FIG. 1( c)stand for the average potentials of the four sections of the surfacevoltage-sustaining region respectively. V₀ is FIG. 1( c) stands for thehighest potential of the voltage-sustaining region of the device.

Note that according to Ref. [1] and Ref. [2], there is a method toobtain an approximate optimum variation lateral doping. That is, it isonly required that in an area with dimension much smaller than W_(pp),the average value of electric flux density emitted from the surfacevoltage-sustaining region into the substrate is approximately equal tothe F(x), shown in FIG. 1( b). FIG. 2( a) shows schematically thestructure of a lateral MOST, where D, S and G stand for drain, sourceand gate electrodes respectively. The shaded area 101 in this figure isthe gate oxide layer or gate insulator layer. Drain electrode D isconnected to n⁺-drain region 012, source electrode S is connected ton⁺-source region 013 and through p⁺-region 014 directly connected top⁻-substrate 001. An oxide layer 102 is set on the top of semiconductorsurface 100, and a conductive metal or heavily-doped polysilicon 103forming a field plate is set on the top of 102. This field plate isconnected to the source electrode S through outer connection 106 shownalso in FIG. 2( a). A MOS capacitor with average value varied withdistance x, which is shown as the abscissa of an x-axis in FIG. 2( a),can be made by varying the fill factor r of the field plate. Since thecapacitance between the field plate and semiconductor surface 100 inunit area is ε_(OX)/t_(OX), where ε_(OX) is the permittivity of theoxide layer and t_(OX) is the thickness of oxide layer, the averagevalue of the capacitance in unit area, C(x), is r×ε_(ox)/t_(ox). FIG. 2(b) shows a top view of the field plate having such a variation ofcapacitance. This field plate has four sections, each section has awidth of d. In the leftmost portion, the value of r is the smallest.Then, the value of r increases towards the right direction. In therightest portion, r has its maximum value, 1. According to FIG. 1( c)and FIG. 1( b), the semiconductor surface should have a voltage V(x) anda flux density flow of F(x) to the substrate, it turns out that

${r \times {ɛ_{ox}/t_{ox}}} = \frac{q\left( {D_{0} - {D(x)}} \right)}{V(x)}$

since the condenser made by the field plate should take a flux densityof q(D₀−D(x)), where qD₀ is the flux density produced by the n-region011 and qD(x)=F(x) is the flux density needed to flow into thesubstrate. Obviously, the closer the place to the drain is, the largerthe value of V(x) is, and thus the smaller the values of (D₀−D(x)) and rare.

The average electric flux densities need to be extracted by the foursections of field plates of FIG. 2 have been already shown in FIG. 1( b)and denoted as ΔF₁, ΔF₂, ΔF₃ and ΔF₄ respectively. From FIG. 1( c), theaverage values of the surface potential of these four sections can befound as V₁, V₂, V₃ and V₄, respectively. Thus, the values of r at thesefour sections can be determined.

Obviously, an equivalent circuit of the four capacitances C₁ C₂, C₃ andC₄ with respect to the corresponding potentials V₁, V₂, V₃ and V₄ can beexpressed and is shown in FIG. 2( c).

However, the above method may not be appropriate in some cases. Forinstance, when the value V(x=0) of the device is very large but theavailable t_(ox) is not large enough, then the field in the oxide can belarger than the dielectric strength. Also, when the fill factor is verysmall, then a very high field may be produced at the tip or the corneror the edge of the interdigitated plate field plate. Note that once thelocal field exceeds the field strength of the oxide, then breakdownoccurs and damage induced is irreversible.

In order to overcome that problem, the multiple conductive layersexisting in many CMOS technologies can be used, so that the thickness ofoxide layer can be varied and the necessory capacitance variation can berealized. FIG. 3 shows an example of such a method applied to a lateralMOST, where D, S and G are drain, source and gate electrodesrespectively. The shaded area 101 is the gate oxide layer or gateinsulator layer. Drain electrode D is connected to n⁺-drain region 012,source electrode S is connected to n⁺-source region 013 and throughp⁺-region 014 connected directly to the p⁻-substrate 001. The structureconsists of a field plate 104 and a dielectric layer 105 underneath itto separate it from the semiconductor. The dielectric layer 105 has foursections with different thicknesses. This field plate has an outerconnection 106 connected to the source electrode, making its potentialto be the same as the substrate, i.e., equals to zero. Such a fieldplate having a terrace structure is called terrace field platehereinafter. The marks C₁, C₂, C₃ and C₄ stand for the capacitance inunit area between the sections of the field plate and the semiconductorsurface. Thus, FIG. 2( c) can be applied to this case. Clearly, thevalues of the capacitances C₁, C₂, C₃ and C₄ should be increased in thatorder and the applied voltage V₁, V₂, V₃ and V₄ decreases in that order.Therefore, the flux density absorbed from the surface of thesemiconductor by the plate increases from the subscript 1 to subscript4.

Of course, the field plate in FIG. 3 can also be made with the fillfactors varies from 0 to 1, similar to that shown in FIG. 2( b).

In order to avoid the field at the places of tips or corners or edges ofthe strip of field plate being too large, floating field plate can beused as shown in FIG. 4( a). This figure schematically shows a structureof lateral MOST, where D, S and G are drain, source and gate electrodesrespectively. The shaded area 101 is the gate oxide layer or gateinsulator layer. D is connected to n⁺-drain region 012, S is connectedto n⁺-source region 013 and also connected to p⁻-substrate 001 viap⁺-region 014. The topmost field plate 104 is formed in aninterdigitated shape shown like in FIG. 2( b). There are three fieldplates under it, namely, 107, 108 and 109. Their layouts are notinterdigitated. From the semiconductor surface to the topmost fieldplate, there are two capacitances in series connection, which isequivalent to one capacitance. The equivalent circuit of such case isalso like FIG. 2( c) shown.

Another method to make floating field plates have the similar effect ofFIG. 4( a) is shown in FIG. 4( b). In this figure, a multiple layer offloating field plates is used. In the leftmost portion of the surfacevoltage-sustaining region, it has two floating field plates 110 and 111placed above the first floating field plates 107. Besides, there is onegrounded field plate 104 at the top. Next to the leftmost, there are twofloating field plates 110 and 111, and one topmost 104. Still next,there is only one floating field plate 111 under the grounded plate 104.Note that the first floating field plate 107 absorbs electric flux ΔF₁of the leftmost shaded portion of FIG. 1( b), this flux should releaseto the floating field plate 110 since 107 should be neutral as a whole.In addition to that flux, the plate 110 also absorbs a flux of ΔF₂ shownin next to the leftmost shaded portion of FIG. 1( b). Therefore, thefloating field plate 110 must emit a sum of both fluxes to the floatingfield plate 111. A similar argument of 110 can be applied to 111. Itturns out that the floating field plates absorb more and more flux fromthe semiconductor according to the order of 107, 110, 111. If all thevoltages between every two neighboring floating field plates are thesame, then the coupling capacitance should be increased in the sameorder. FIG. 4( b) satisfies such a requirement.

In the case of some coupling capacitance of FIG. 4( b) needed to be evensmaller, then one can use the method shown FIG. 2( b).

Of course, the number of sections of the surface voltage-sustainingregion is not necessary being four, it can be more or less. Thethickness of the oxide layer also can be different. Moreover, thesilicon dioxide can be replaced by other insulator layer. Especially, itis not necessary for the semiconductor surface voltage-sustaining regionto have a uniform doping density. It should also be pointed out thataccording to Ref. [1, 2 and 3], the average electric flux densityemitted from the surface voltage-sustaining region means an averageeffective value taken in a size much smaller than W_(pp).

However, the method shown in FIG. 4( b) may still have problem in thatthe maximum available thickness of the oxide layer is still not enoughto sustain a high voltage. For example, if the maximum thickness t_(ox)of the oxide is 1 μm, i.e., t_(ox)=1 μm, and the dielectric strength is5×10⁶ V/cm, the voltage can be achieved is 500V and the flux density canbe absorbed by the field plate is F=ε_(ox)×V/t_(ox), where ε_(ox) is thepermittivity of silicon dioxide and equals to 3.9×8.85×10⁻¹⁴ F/cm. Thus,the flux density can be absorbed is equivalent to a dose of impurity ofF/q=1×10¹³ cm⁻². This flux density is normally too large.

In order to overcome this restriction, some methods stated in thefollowing are proposed in this in invention.

FIG. 5( a) shows an example of using a number of n of floating fieldplate (P₁, P₂, P₃, . . . P_(n−1), P_(n)) and one grounded field plateP_(G) to form a high-voltage diode, where A and K stand for anode andcathode respectively. The cathode K is connected to n⁺-region 012 andthe anode A connected to p⁺-region 014. If the voltage can be sustainedbetween each field plate and the semiconductor surface is ΔV and thatbetween two neighboring field plates is ΔV_(F), then the total voltagecan be sustained between cathode K and the substrate is n×ΔV_(F)+ΔV,which increases as the number n increases.

Since floating field plates with potential close to the substrate shouldhave larger coupling capacitance, FIG. 5( a) cannot satisfy such arequirement.

Yet, larger coupling capacitances can be fulfilled by extending to thearea outside of the voltage-sustaining region. FIG. 5( b) showsschematically a high-voltage diode by using such a method, where A and Kare the anode and cathode electrodes respectively. Cathode K isconnected to n⁺-region 012 and anode A is connected to p⁺-region 014.This device has a grounded field plate 116 and floating field plates112, 113, 114 and 115, where 114 is connected through outer connection119 to plate 118 and 115 is connected through outer connection 120 toplate 117.

FIG. 5( c) shows another example of using multiple floating fieldplates. It is somewhat similar to FIG. 5( a) except that such astructure can use less number of plates under the same breakdownvoltage. In other words, with floating field plates of number n, thetotal voltage can be sustained is (n+1)ΔV_(F)+ΔV now. In comparison withFIG. 5( a), the effect is like an increase of an additional floatingfield plate of FIG. 5( a).

An estimation of the parameters of the field plates shown in FIG. 5 canbe done by referring the equivalent circuit showing in FIG. 6. In thisfigure, C_(i) (i=1, 2, 3, . . . n) stands for the capacitance in unitarea between the i-th plate and the semiconductor surface, d_(i) (i=1,2,. . . n) stands for the width of the i-th section, ΔF_(i) and V_(i)stand for the average electric flux density extracted from the i-thsection of the semiconductor surface and the average surface potentialrespectively. The average potential of the semiconductor surfacedecreases according to the order of i=1, 2, 3, . . . . Thus, the voltageacross the capacitor C_(i) is

V _(i) −U _(i) =ΔF _(i) /C _(i)

Where U_(i) is the potential of the i-th floating field plate. It turnsout that the voltage across the coupling capacitor C_(i,i+1) between thei-th plate and the (i+1)-th plate is

(U _(i) −U _(i+1))=V _(i) −V _(i+1)−(ΔF _(i) /C _(i) −ΔF _(i+1) /C_(i+1))

Since the increment of the charge of the coupling capacitor in unit areacaused by the i-th section is ΔF_(i) and the charge on the couplingcapacitor is the sum of the charge absorbed by the i-th section andcharges absorbed by all sections before it, the charge on C_(i,i+1) is

ΔF₁+ΔF₂+ . . . +ΔF_(i)

It turns out that the value of C_(i,i+1) is

C _(i,i+1)(ΔF ₁ +ΔF ₂ + . . . +ΔF _(i))/(U _(i) −U _(i+1))=(ΔF ₁ +ΔF ₂ +. . . ΔF _(i))/(V _(i) +ΔF _(i) /C _(i) −V _(i+1) −ΔF _(i+1) /C _(i+1))

The estimation values of C_(i,i+1) can be taken as a first approximationfor a numerical simulation to obtain the more precise values.

Obviously, the field plates can also introduce electric flux into thesemiconductor. FIG. 7( a) shows an example of high-voltage n⁺-p diodemade on a p⁻-substrate 001, where A and K has the same meanings asbefore. K is connected to n⁺-region 12 and A is connected to p⁺-region014. There is no surface n-region in the surface voltage-sustainingregion. The only n⁺-region 012 is for cathode contact, which is notincluded in the surface voltage-sustaining region. In this example, onefield plate 121 connected to the cathode K and the remaining three fieldplates, 122, 123 and 124, are floating. The surface has four sections,the leftmost field plate 121 has a potential higher than the averagepotential V₁ of the semiconductor surface, and therefore introducedelectric flux from the field plate through the oxide layer under it,then into the semiconductor. This plate has a potential higher than thatof the floating field plate 122, so, some flux flow from 121 throughoxide layer above it and then into 122. The floating field plate 122 hasa potential in turn higher than the average potential V₂ of thesemiconductor surface below it, so some flux flow from 122 into thesecond section of semiconductor surface, and so on and so forth.

FIG. 7( b) shows another example. This structure has a field plate 125,connected to the cathode K and three floating field plates 126, 127 and128. Although the total number of plates is the same as FIG. 7( a), thevoltage can be sustained here is 4×ΔV_(F)+ΔV, whereas in FIG. 7( a), itis 3×ΔV_(F)+ΔV.

FIG. 7( c) shows the equivalent circuit applicable to both FIG. 7( a)and FIG. 7( b). Where C_(i) represents the product of the capacitance inunit area times the width of section i, this product equivalent toC_(i)d_(i) shown in FIG. 6. C_(i,i+1) in FIG. 7( c) represents thecapacitance between the i-th floating field plate and the (i+1)-thfloating field plate in a unit length perpendicular to the paper. V_(i)and U_(i) have the same meanings as in FIG. 6 and V₀ is the cathodevoltage of the diode. Evidently, for the case of FIG. 7( a), U₁=V₀. Forthe case of FIG. 7( b) C₁=0, i.e., C₁ does not exist.

The voltage across C_(i) is U_(i)−V_(i), which makes a electric fluxF_(i)=(U_(i)−V_(i))×C_(i) to the semiconductor surface in unit lengthperpendicular to the paper, corresponding to ΔF_(i)×d_(i) in FIG. 6.

Obviously, the voltage across the coupling capacitor C_(i+1) is

(U _(i) −U _(i+1))=V _(i) −V _(i+1) +F _(i) /C _(i) −F _(i+1) /C _(i+1)

And the charge on C_(i,i+1) is the sum of charges on the field platesstarting from the (i+1)-th section to the last field plate, i.e.,

F_(i+1)+F_(i+2)+ . . . +F_(n)

Thus, the value of C_(i,i+1) needed can be determined by the followingequation:

C _(i,i+1)=(F _(i+1) +F _(i+2) + . . . +F _(n))/(U _(i) −U _(i+1))

In above, the potentials of each floating field plates are supposed tobe certain values when the diode or the MOST is under a certain reversevoltage. However, if the insulator layer is not perfect, then a leakagecurrent occurs and the floating field plates will be charged ordischarged. Eventually, the values of potentials of the floating fieldplates cannot be the values required when the voltage applied to thedevice varies.

One method to avoid such effect is to use an outer circuit to switch allof the floating field plates to the ground, namely to the substrate,during the device is turned-on with the voltage across the surfacevoltage-sustaning region being very low or when it is not been used.Another method is to use an outer circuit to connect all floating fieldplates to required potentials. Then the plates are not floating anymore.

This invention provides an approach to solve the leakage problem. Themethod is to connect each plate to a floating field limiting ring.Needless to say, a field plate connected only to a floating fieldlimiting ring is still a floating field plate. FIG. 8 shows examples ofsuch method. FIG. 8( a) shows schematically a structure of a highvoltage lateral n⁺-p diode made on a p⁻-substrate 001, wherein floatingfield limiting rings are set. In this figure, A and K represent anodeand cathode electrodes respectively. A is connected to p⁺-region 014 andto field plate 131 as well. The plates 129 and 130 are connected top⁺-floating field limiting rings 015 and 016 respectively. When thecathode K has a high positive potential with respect to the anode A,each p⁺-floating field limiting ring has a negative potential incomparison to the n-region on its right side, this is because some holeshave left the p⁺-ring and flown to the place of lower potential.However, the p⁺-floating field limiting rings can only have about onevolt less than its neighboring n-region because it becomes difficult toinject holes to the neighboring n-region when the potential barrier ismuch larger than one volt. Note that one volt is much less than thevoltage across the voltage-sustaining region in high-voltage devices andcan be neglected.

Thus, suppose the width and the thickness of each floating fieldlimiting ring are much smaller than those of its enclosing n-region inthe surface voltage-sustaining region, then the structure shown in FIG.8( a) can achieve a breakdown voltage of that of an ideal VLF, so far asall the p⁺-rings have been placed correctly.

A little leakage current between a field plate and the semiconductorsurface has little influence to the potential of the field plate, in thecase of that the field plate is connected to a floating field limitingring. To make this in effective, it is appropriate to set the fieldlimiting rings only in certain portions of an area instead of all areahaving a certain potential. FIG. 8( b) shows an example of finger edgeof a surface voltage-sustaining region where there is no floating fieldlimiting ring. The rings are set at the finger ends. The cross-sectionview of such ends can also be represented by FIG. 8( a). Then the topview of such ends is shown in FIG. 8( c). In this top view, floatingfield limiting rings cannot be shown because they are covered by plates.Actually, there are two floating p⁺-rings, 015 and 016, at the fingerend; they have potentials U₁ and U₂, respectively. Two field plates, 129and 130, are placed on them. The ring 015 and ring 016 do not exist inthe finger edge.

FIG. 9 shows schematically a lateral MOST using above method, where, onthe p⁻-substrate 001, an n-type region 011 constructs thevoltage-sustaining layer. The marks D, S and G stand for drain, sourceand gate electrodes respectively. The shaded area 101 is gate oxidelayer or gate insulator layer. The drain electrode D is connected to then⁺-drain region 012, the source electrode S is connected to n⁺-sourceregion 013 and p⁺-region 014, thus connected to the p⁻-substrate 001.This device has two terrace field plates 132 and 133. FIG. 9( a) showsthe structure at the finger edge, where the terrace field plates 132 and133 are connected to two p⁺-floating field limiting rings 015 and 016.These two rings are set at the finger end shown in FIG. 9( b).

The field plates can be connected to some floating field limiting ringsthat are set in other device instead of in the device itself. FIG. 10(a) shows an example to illustrate this point. In this figure, there aretwo lateral diodes. The device in the left dash-dotted block, 201, is asmall round n⁺-p diode, which is not an interdigitated layout. Thedevice in the right dash-dotted block, 202, is a large n⁺-p diode, hasan interdigitated layout. In both devices, A and K are anode electrodeand cathode electrode, respectively. The cathode electrode K isconnected to n⁺-region 012. The anode electrode A is connected top⁺-region 014. The floating field limiting rings, p⁺-region 015 and 016,are connected with terrace field plates 132 and 133 respectively. Thefield plates 132 and 133 of the small device 201 are connected to thefield plates 132 and 133 of the large device through outer connections.FIG. 10( b) shows the top view with outer connections of both 132 andboth 133. Both devices are applied with the same voltage and thefloating field limiting rings produce certain voltages to the fieldplates. When the devices have no applied voltage on them or when theyare conducting and the voltage across the surface voltage sustainingregion is very small, then all potentials of the floating field limitingrings are set to a very small value. The charges of the floating fieldplates, if any, can be lead to the substrate.

The examples of surface voltage-sustaining region so far are limited toeither a case of an n-region (011) being dosed heavier than that in theideal case, or a case of no n-region in the surface voltage-sustainingregion at all (FIG. 7). It is apparent that, basically, the techniquespresented in this invention can be applied to other complicated cases,e.g., an n-region existing only partly in the surface voltage-sustainingregion; or a non-uniformly dosed n-region in the surfacevoltage-sustaining region; or a combination of n-regions and p-regionsin the surface voltage-sustaining region, etc., etc.

It is also evident that the variation of the capacitance in unit area isnot restricted to only by variation of the fill-factor of the fieldplate(s) and/or the total thickness of the insulator layer. It can alsobe made by a variation of electric permittivity of the insulator, or usethis as an additional measure.

Although the examples of the devices discussed so far are based onp⁻-substrate, needless to say, the principle can be applied to devicesbased on n-substrate.

The surface voltage-sustaining region by taking advantage of optimumvariation flux with help of field plates can not only be applied todevices with one electrode connected to the substrate, but also beapplied to high-sided devices in totem pole configuration. FIG. 11 showsan example to use such technique for making a high-side n-MOST and alow-side n-MOST. The left part of the figure is a high side n-MOST, theright part is a low-side n-MOST. Both devices are made on ann⁻-substrate 002. The surface voltage-sustaining regions of both devicesinclude p-region 017 and n-region 019. An n-type region 003 is placedbetween the two surface voltage-sustaining regions. The symbols D, S andG stand for drain, source and gate electrodes, respectively, whereas thesubscript H represents high side and L represents low side. The drainelectrode D_(L) of the low-side MOST is connected to n⁺-drain region019, the source electrode S_(L) of the low-side MOST is connected ton⁺-source region 020, and connected to source-body p-region 018 throughp⁺-region 021. The drain electrode D_(H) of the high-side MOST isconnected to n⁺-drain region 022, the source electrode S_(H) of thehigh-side MOST is connected to n⁺-source region 023 and connected tosource body p-region 018 through p⁺-region 024. The surfacevoltage-sustaining region of the low-side MOST has three terrace fieldplates, namely 134, 135 and 136, where 136 is connected to sourceelectrode S_(L) through outer connection, 134 and 135 are connected tothe floating field limiting rings, 025 and 026, respectively. Similarly,the surface voltage-sustaining region of the high-side MOST has alsothree terrace field plates, namely 137, 138 and 139, where 139 isconnected to source electrode S_(H) through outer connection, 138 and139 are connected to the floating field limiting rings 027 and 028respectively.

The structure shown in FIG. 11 is similar to FIG. 14 of Ref. [5] in itsfunction. FIG. 14 of Ref. [5] is a modification of FIG. 11 of thatreference for increasing the dose of n-drift region and thus to decreasethe specific on-resistance, where the effect of an increment of dose iscompensated by the p-region on its top. In this invention, a remainingof dose of n-drift region is offset by the flux taken out from thesemiconductor surface by the field plate.

As pointed out in Ref. [4] and Ref. [5], an isolation region isnecessary in between the high-side and the low-side. In FIG. 11, thisisolation region is constructed by the region starting from the left ofp⁺-region 021 of low-side device to the right of n⁺-region 022. A fieldplate 140 is covered on this isolation region and also makes aconnection between S_(L) and D_(H). This field plate helps to isolatethe high-side and the low-side by changing the flux of the n-region 003through isolation layer 141.

Naturally, the technique proposed by this invention can also be appliedto the case that an insulator exists between the substrate and thesurface voltage-sustaining region. FIG. 12 shows an example of thiscase. The difference to FIG. 11 is only in that an insulator (I) layer,004 separates the surface voltage-sustaining region and the substrate.

Of course, the techniques proposed in this invention can be applied notonly to lateral diode and lateral MOST, but also to other lateraldevices. Even more, they can be used to be an edge termination techniquefor vertical devices.

Besides, the technique of bird beak in integrated circuit can be used tofield plates to avoid producing a local high electric field around thetip or the corner or the edge.

The techniques proposed by this invention have been illustrated by manyexamples of applications. It should be understood that various changesand modifications to the presently preferred embodiments describedherein will be apparent to those skilled in the art. Such changes andmodifications may be made without departing from the spirit and scope ofthe present invention and without diminishing its attendant advantages.It is therefore, intended that such changes and modifications be coveredby the appended claims.

1. A semiconductor lateral device comprising: a lightly-dopedsemiconductor substrate of a first conductivity type; a device edgeregion of semiconductor of a first conductivity type on a semiconductorsurface; a device central region of semiconductor of a secondconductivity type on said semiconductor surface and located in a centralpart of an area enclosed by said device edge region; a surfacevoltage-sustaining region, extended from said device central region tosaid device edge region, and including: at least one section ofinsulator layer, having a lateral variation of electric permittivityand/or thickness, covering on said semiconductor surface; at least oneconductive layer covering at least partly on said insulator layer,forming terrace field plate(s); said surface voltage-sustaining regionmay have one or more than one thin semiconductor surface region(s)having a different doping concentration and/or a different conductivitytype from that of said substrate; said surface voltage-sustaining regionis fully depleted under a maximum reverse voltage close to a breakdownvoltage applied between said central region and said edge region; saidterrace field plate(s) and the semiconductor surface form two plates ofa capacitor with a capacitance in unit area being proportional to both apermittivity of said insulator and a fill factor of said plate, andinversely proportional to a thickness of said insulator; an electricflux at a place which flows from said semiconductor into said terracefield plate with a density of flux proportional to voltage drop fromsaid semiconductor surface to said terrace field plate and proportionalto said capacitance in unit area at said place; an electric fluxdensity, under an action of an effective density of said electric fluxproduced by all charges of said depleted semiconductor surface region(s)in said surface voltage-sustaining layer and an action of said electricflux flow to said terrace plate(s), emitted from said surfacevoltage-sustaining region into said substrate decreasing gradually orstepwisely from a value of about 2ε_(S)V_(B)/W_(pp) to a value of aboutzero with the increasing of distance from said central region; whereε_(S) is a permittivity of the semiconductor, V_(B) is said maximumreverse voltage and W_(pp) is a depletion width of an one sided abruptparallel plane junction made by said substrate under reverse voltageV_(B); said flux density, said capacitance in unit area and said voltagedrop from said semiconductor surface to said terrace field plate meanaverage values of said parameters, where said average values are takenin an area having a lateral dimension smaller than W_(pp); said surfacevoltage-sustaining layer has a vertical dimension smaller than W_(pp);wherein when said substrate is a p-type semiconductor, said electricflux means a flux generated by positive charges, and both said reversevoltage applied between central region and said edge region and saidvoltage drop from said surface to said terrace field plate are positivevoltage; wherein when said substrate is an n-type semiconductor, saidelectric flux means a flux generated by negative charges, and both saidreverse voltage applied between central region and said edge region andsaid voltage drop from said surface to said terrace field plate arenegative voltage.
 2. A semiconductor device according to claim 1,wherein said terrace field plate is covered at least in part by aninsulator layer on its top, said insulator is in turn covered by aconductive layer which is connected to a neighboring terrace fieldplate; a capacitor is therefore formed between two neighboring fieldplates and an electric flux flows from a field plate having a largerpotential to a field plate having a smaller potential.
 3. Asemiconductor device according to claim 1, wherein said semiconductorregion(s) in said surface voltage-sustaining region has at least oneregion of a conductivity type located on a top of another region ofdifferent conductivity type, where the former region has smaller lateraland vertical sizes than those of the latter, is not fully depleted andremains partly a neutral and floating region under said reverse voltagebeing applied across said surface voltage-sustaining region, whereineach neutral and floating region is connected to a part of a terracefield plate located most close to it.
 4. A semiconductor deviceaccording to claim 1, wherein a terrace field plate is connected to saidedge region of said voltage-sustaining region at a portion of said platewhich is located closest to said edge region.
 5. A semiconductor deviceaccording to claim 1, wherein a terrace field plate is connected to saidcentral region of said voltage-sustaining region at a portion of saidplate which is located closest to said central region.
 6. Twosemiconductor devices each according to claim 1, wherein both cansustain the same reverse voltage; and one has a larger surface area,another has a smaller surface area; wherein said smaller surface areadevice has at least one region of a conductivity type located on a topof another region of different conductivity type, where the formerregion has smaller lateral and vertical sizes, is not fully depleted andremains partly a neutral and floating region(s) when said reverse regionis applied across said surface voltage-sustaining region; wherein eachterrace field plate of said smaller area device is connected to certainfloating region at place most close to it; wherein each terrace fieldplate of said larger area device is connected to a certain terrace fieldplate of said smaller area device through outer connections.
 7. Asemiconductor device according to claim 1, wherein said lateral deviceis a low-side high voltage MOST or a high-side high voltage MOST.
 8. Asemiconductor device according to claim 1, wherein said device is alateral diode, wherein: said central region is a cathode region and saidedge region is an anode region if said substrate is a p-typesemiconductor; said central region is an anode region and said edgeregion is a cathode region if said substrate is an n-type semiconductor.9. Two semiconductor devices, each according to claim 1, wherein saiddevices are a lateral low-side device and a lateral high-side device;wherein an insulator layer is between said surface voltage-sustainingregion and said substrate; said substrate has an outer connection toconnect with said edge region of said low-side device.
 10. Asemiconductor vertical power device, wherein edge termination is made bya surface voltage-sustaining region according to claim 1.